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vhdl generic

Puzzled Panda answered on March 16, 2023 Popularity 6/10 Helpfulness 6/10

answer vhdl generic

vhdl generic

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vhdl generic

entity RAM is
generic(
 data_width : integer := 64;
 addr_width : integer := 12;
 Taa : time := 50; 
 Toe : time := 40); 
port(
 oeb, wrb, csb : in std_logic;
 data : inout std_logic_vector(data_width-1 downto 0);
 addr : in std_logic_vector(addr_width-1 downto 0));
end RAM;

RAM1 : RAM 
generic map(
 data_width => 32,
 addr_width => 20,
 Taa => 30 ns,
 Toe => 35 ns)
port map(
 oeb => oeb, wrb => wrb, csb => csb,
 data => data ,
 addr => addr );

Popularity 6/10 Helpfulness 6/10 Language python

Source: Grepper

Tags: python vhdl

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Contributed on Mar 16 2023

Puzzled Panda

0 Answers Avg Quality 2/10

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